All lead systems share a primary function: to permit the connection of an integrated circuit chip to an environment of use, such as a circuit board or an electronic device. These external connections cannot be made directly to a semiconductor die due to the thin and fragile nature of the electrical connections within a semiconductor die. Instead, a system of conductive package leads is provided to access the semiconductor die.
As shown in FIG. 1a, a lead system 10 is composed of many individual electrically conductive leads 12. When emplaced in a semiconductor package, each lead is generally continuous from the semiconductor die attach cavity to the printed circuit board or electronic product. The inner portion of a lead (which is proximal to the semiconductor die) is referred to as the inner lead, the bonding lead tip, or the inner bond finger 14. The mid-portion of the lead, which generally remains planar during packaging procedures, is referred to as the lead body 15. The outer portion of the lead (which is distal from the semiconductor die) is referred to as the outer lead 16, or, if appropriate, the package lead. FIG. 1b shows an end view of inner bond fingers 14 of the prior art, taken along line 1b--1b of FIG. 1a. FIG. 1c shows a cross-sectional view of a planar individual lead taken through line 1c--1c of FIG. 1a. In some packaging schemes, such as DIP, MQUAD, and the like, the outer lead 16 would be bent to form package leads (not shown). The outer lead 16 would thus be removed from the generally planar configuration of the lead body 15 and the inner bond finger 14. In other packaging schemes, such as chip-on-tape, leaded chip carrier package, and the like, the outer lead 16 would remain planar with the lead body 15 and the inner bond finger 14.
The lead system 10 may include a die attach pad (not shown). The lead system 10 can be made from a solid piece of conductive material, which is etched, stamped, or otherwise processed to form individual leads 12. In some applications, the lead system is formed on a non-conductive layer or uses a non-conductive tape structure, such as a polyimide layer (not shown), to maintain individual leads in position during processing.
Some prior art packaging systems maintain a substantially planar lead configuration throughout manufacturing, packaging, and use. Examples include leaded chip carrier packages, in which lead pins are electrically attached to the planar lead structure, and chip-on-tape packages. Other packaging schemes conform the outer leads 16 to yield package leads. Examples include DIP and MQUAD packages. However, in each of these prior art packaging schemes, the lead system which is housed within the package itself, i.e., the lead body 15 and the inner bond fingers 14, have been held in a uniform, generally planar, position throughout the manufacturing process.
FIG. 2 shows a cross-sectional view of a wirebond semiconductor package 20, in which the electrical connection between an individual bonding pad of the semiconductor die and an electrically conductive lead 12 is made using a thin connecting wire, the bond wire 22. The bond wire 22 is bonded at one end to a die bonding pad on the semiconductor die (for die input or output), and at the opposite end to an inner bond finger 14. In the pictured embodiment, each lead 12 include an inner bond finger 14, a lead body 15, and an outer lead 16, which has been processed to form a package lead.
The wirebond semiconductor package 20 generally includes a rigid protective housing 24 which surrounds the semiconductor die 18. The housing 24 is usually filled with a liquid potting mixture, or other encapsulant (not shown), which then hardens in situ. During the introduction of the liquid, however, the bond wires 22 are susceptible to mid-line motion or "sweep". As the fill liquid is introduced across the wires from a given direction, bond wires 22 which are parallel to the liquid flow are minimally disturbed. However, bond wires 22 which are perpendicular to (across) the flow of the liquid are easily bent out of position along the curve of the wires. Closely-spaced adjoining bond wires can be "swept" into a position in which they touch. As the liquid fill material solidifies, the touching bond wires can provide a permanent short-circuit of the semiconductor package, causing the semiconductor package to fail.
A variety of approaches have been put forward to minimize or eliminate the bond wire "sweep". The direction of the fill material entry ("top gating" and "bottom gating", for example) has been varied to minimize sweep.
"High/low bonding" has also been used to minimize sweep effects. This bonding pattern uses bonding wire loops of different lengths and heights to help maintain separation between the individual bonding wires. Both the "high" and the "low" bond wires in traditional high/low bonding patterns are fixed in a single plane at the semiconductor die and at another single plane at the lead system. While high/low bonding patterns provide increased separation between bonding wires during the bonding procedure itself, there are significant drawbacks to the system during the fill phases. The "high" bond wires have increased length, and thus are more flexible than the "low" bond wires. During a fill process, the "high" bond wires are easily flexed out of their original position and into a shorting relationship with adjacent wires. As noted above, when the bond wire length is in the same direction as the flow direction of the fill material, the problem is somewhat reduced. However, this problem is especially critical when high/low bond wires are located 90.degree. from the source of the fill material.
The prior art bonding patterns and systems have not provided an adequate wire bonding pattern to minimize shorting during fill processes. Specifically, prior art wire bonds tend to short during fill procedures when closely positioned adjacent wires touch.